Previous Designs

Chip Boards

NNHDS Previous Designs

  • Conversion of a schematic capture-based design to HDL targeting an SoC
  • Principal contributor for custom protocol IP design and verification
  • Principal contributor for next-generation ROIC test electronics
  • Hardware validation lead for IR cameras
  • Design lead for a 2048 x 2048 two-color IR camera
  • Design lead for a 3072 x 3072 two-color IR camera
  • Design lead for a 6192 x 4096 single-color IR camera
  • Design lead of a custom DDR3 SDRAM controller for a memory backup application
  • Design lead of a custom DDR2 SDRAM controller for a memory backup application
  • Verification lead of a custom video encoder
  • Verification lead of a networking switch fabric chip
  • Design contributor of a dual-PPC application
  • Design contributor of a PCI-to-PCI bridge
Circuit Board
  • Hardware validation contributor of a UDP packet validation unit
  • Principal supporter of IP, including maintenance and updates: UDP stack, UL2 Link, UL2 PHY, PL3 Link, PL3 PHY, PL4
  • Design lead to customize an SDRAM controller
  • Design lead of a custom UL2 to PL3 cell switch
  • Design contributor of a PL4 to XAUI bridge
  • Principal contributor to define an enhanced VHDL testbench and drive its implementation
  • Design contributor of a USB-CBUS/MBUS bridge
  • Principal contributor to a packet processor verification effort
  • Principal contributor of a HyperTransport dual link tunnel device
  • Design and verification contributor of broadband ASICs utilizing ATM, SONET/SDH, POS and Ethernet
  • Design contributor of an SCM-to-PCI bridge
  • Technology remap of a PCI ASIC
  • Conversion of design EDIF to HDL of a SONET transmitter and SONET receiver
Hardware Engineering.
  • Design contributor of a look-up engine
  • Design and verification contributor of an Ethernet/FDDI controller
  • Design contributor of a route look-up ASIC
  • Design contributor of an AMBA-ASB-based cache controller
  • Verification of a DDR-SDRAM controller
  • Design of an IPv4 packet validation unit
  • Verification of a CORE to POS-PHY Level 3 bridge
  • Verification of a POS-PHY Level 3 to CORE bridge
  • Verification of a quad UTOPIA/POS-PHY Level 2 to UTOPIA/POS-PHY Level 3 bridge
  • Verification of a UTOPIA/POS-PHY Level 2 to UTOPIA/POS-PHY/ANY-PHY Level 3 bridge